The present invention relates generally to integrated circuit technology, and particularly to a silicon carbide gate transistor, such as a floating gate transistor, and complementary metal-oxide-semiconductor (CMOS) compatible methods of fabrication, and methods of use in memory and light detection devices.
Field-effect transistors (FETs) are typically produced using a standard complementary metal-oxide-semiconductor (CMOS) integrated circuit fabrication process. Such a process allows a high degree of integration for obtaining high circuit density with relatively few processing steps. Resulting FETs typically have gate electrodes composed of n-type conductively doped polycrystalline silicon (polysilicon) material.
The intrinsic properties of the polysilicon gate material affects operating characteristics of the FET. Silicon (monocrystalline and polycrystalline) has intrinsic properties that include a relatively small energy bandgap (Eg), e.g. approximately 1.2 eV, and a corresponding electron affinity ("khgr") that is relatively large, e g. "khgr"≈4.2 eV. For example, for p-channel FETs fabricated by a typical CMOS process, these and other material properties result in a large turn-on threshold voltage (VT) magnitude. As a result, the VT magnitude must be downwardly adjusted by doping the channel region that underlies the gate electrode of the FET.
Conventional polysilicon gate FETs also have drawbacks that arise during use as a nonvolatile storage devices, such as in electrically erasable and programmable read only memories (EEPROMs). EEPROM memory cells typically use FETs having an electrically isolated (floating) gate that affects conduction between source and drain regions of the FET. A gate dielectric is interposed between the floating gate and an underlying channel region between source and drain regions. A control gate is provided adjacent to the floating gate, separated therefrom by an intergate dielectric.
In such memory cells, data is represented by charge stored on the polysilicon floating gates. Fowler-Nordheim tunneling is one method that is used to store charge on the polysilicon floating gates during a write operation and to remove charge from the polysilicon floating gate during an erase operation. However, the relatively large electron affinity of the polysilicon floating gate presents a relatively large tunneling barrier energy at its interface with the underlying gate dielectric. The large tunneling barrier energy provides longer data retention times than realistically needed. For example, a data charge retention time at 85xc2x0 C. is estimated to be in millions of years for in some floating gate memory devices. The large tunneling barrier also increases the time needed to store charge on the polysilicon floating gates during the write operation and the time needed to remove charge from the polysilicon floating gate during the erase operation. This is particularly problematic for xe2x80x9cflashxe2x80x9d EEPROMs, which have an architecture that allows the simultaneous erasure of many floating gate transistor memory cells. Since more charge must be removed from the many floating gates in a flash EEPROM, even longer erasure times are needed to accomplish this simultaneous erasure. There is a need in the art to obtain floating gate transistors allowing faster storage and erasure, such as millisecond erasure periods in flash EEPROMs.
Other problems result from the large erasure voltages that are typically applied to a control gate of the floating gate transistor in order to remove charge from the floating gate. These large erasure voltages are a consequence of the large tunneling barrier energy between the polysilicon floating gate and the underlying gate dielectric. The large erasure voltages can result in hole injection into the gate dielectric. This can cause erratic overerasure, damage to the gate dielectric, and introduction of trapping states in the gate dielectric. The high electric fields that result from the large erasure voltages can also result in reliability problems, leading to device failure. There is a need in the art to obtain floating gate transistors that allow the use of lower erasure voltages. There is a need in the art for floating gate transistors capable of operating at lower programming and erasure voltages and having improved reliability.
Halvis et al. (U.S. Pat. No. 5,369,040) discloses a charge-coupled device (CCD) photodetector which has transparent gate MOS imaging transistors fabricated from polysilicon with the addition of up to 50% carbon, and preferably about 10% carbon, which makes the gate material more transparent to the visible portion of the energy spectrum. The Halvis et al. patent is one example of a class of conventional CCD photodetectors that are directed to improving gate transmissivity to allow a greater portion of incident light in the visible spectrum to penetrate through the gate for absorption in the semiconductor substrate. However, the absorption of photons in the semiconductor substrate is limited to high energy photons exceeding a bandgap energy of the semiconductor substrate. There is a need in the art to detect lower energy photons independently of the semiconductor bandgap energy limitation. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, the above described needs are unresolved in the art of fabrication of light detection devices, FETs, and EEPROMs using CMOS processes.
Y. Yamaguchi et al., xe2x80x9cProperties of Heteroepitaxial 3Cxe2x80x94SiC Films Grown by LPCVDxe2x80x9d, 8th International Conference on Solid-State Sensors and Actuators and Eurosensors IX, Digest of Technical Papers, page 3. vol. (934+1030+85), pages 190-3, Vol. 2, 1995;
M. Andrieux, et al., xe2x80x9cInterface and Adhesion of PECVD SiC Based Films on Metalsxe2x80x9d, Le Vide Science, Technique et Applications. (France), No. 279, pages 212-214, 1996;
F. Lanois, xe2x80x9cAngle Etch Control for Silicon Power Devicesxe2x80x9d, Applied Physics Letters, Vol 69, No. 2, pages 236-238, July 1996;
N. J. Dartnell, et al., xe2x80x9cReactive Ion Etching of Silicon Carbidexe2x80x9d Vacuum, Vol. 46, No. 4, pages 349-355, 1955.
The present invention includes a transistor having a gate formed of a silicon carbide compound Si1xe2x88x92xCx, wherein x is selected at a predetermined value approximately between 0 and 1.0 to establish a desired value of a barrier energy between the gate and an adjacent insulator. The SiC gate is either electrically isolated (floating) or interconnected. In one embodiment, the gate is an electrically isolated floating gate, and the transistor further includes a control gate, separated from the floating gate by an intergate dielectric.
Another aspect of the invention provides a method of producing a transistor on a semiconductor substrate. Source and drain regions are formed, thereby defining a channel region between the source and drain regions. An insulating layer is formed on the channel region. A gate is formed on the insulating layer. The gate comprises a silicon carbide compound Si1xe2x88x92xCx. The SiC composition x is selected at a predetermined value approximately between 0 and 1.0. In one embodiment, the value of the SiC composition x is selected to establish the value of a barrier energy between the gate and the insulator.
Another aspect of the invention provides light detection. Charge is stored on a floating gate of a transistor. Incident light is received at the floating gate, thereby removing at least a portion of the stored charge from the floating gate by the photoelectric effect. A change in conductance between the transistor source and drain is detected. In one embodiment, the method of detecting light includes selecting at least one wavelength of the incident light to which the floating gate transistor is most sensitive. In another light detecting embodiment, the invention provides a transistor that includes a floating gate separated from a channel region by an insulator. The floating gate is formed of a silicon carbide compound Si1xe2x88x92xCx. The SiC composition variable x is selected at a predetermined value approximately between 0 and 1.0 to establish the wavelength of incident light absorption to which the floating gate is sensitive. Charge is stored on the floating gate. Incident light is received at the floating gate, thereby removing at least a portion of the stored charge from the floating gate by the photoelectric effect. A change in conductance between the transistor source and drain is detected. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.
In another embodiment, the transistor is used in a memory device that includes a plurality of memory cells. Each memory cell includes a transistor having a floating gate separated from the channel region by an insulator. The floating gate is formed of a silicon carbide compound Si1xe2x88x92xCx, wherein x is selected at a predetermined value approximately between 0 and 1.0 to establish a desired value of a barrier energy between the gate and the insulator.
In a flash electrically erasable and programmable read only memory (EEPROM) application, the SiC composition x is selected to provide the desired programming and erase voltage and time or data charge retention time. The lower barrier energy and increased tunneling probability of the SiC gate advantageously provides faster programming and erasure times for floating SiC gate transistors in flash EEPROM memories. This is particularly advantageous for xe2x80x9cflashxe2x80x9d EEPROMs in which many floating gate transistor memory cells must be erased simultaneously. Writing and erasure voltages are also advantageously reduced, minimizing the need for complicated and noisy on-chip charge pump circuits to generate the large erasure voltage. Lower erasure voltages also reduce hole injection into the gate dielectric that can cause erratic overerasure, damage to the gate dielectric, and introduction of trapping states in the gate dielectric. Reducing the erase voltage also lowers the electric fields, minimizing reliability problems that can lead to device failure, and better accommodating downward scaling of device dimensions. Data charge retention time is decreased. Since conventional data charge retention times are longer than what is realistically needed, a shorter data charge retention time can be accommodated in order to obtain the benefits of a smaller barrier energy. The data charge retention time can be selected between seconds and millions of years by selecting the value of the SiC composition x, such as to obtain different memory functionality.